Microprocessors and Microcontrollers: Timing Diagram

T - State

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One sub-division of the operation performed in one clok period is called one T-state.

Machine Cycle
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The time required to complete one operation of accessing either memory or i/o is called one machine cycle. The machine cycle may consist of 3 to 6 T-state.

Instruction Cycle
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The time required to complete the execution of an instruction. An instruction cycle may consist of 1 to 5 machine cycles.

Remember this:

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S1 | S0 | Process

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0 | 0 | Halt

0 | 1 | Write

1 | 0 | Read

1 | 1 | Opcode fetch

First we need to know the Machine Cycles of 8085

Opcode fetch

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• This cycle requires 4 T-states.
• 1st T state ALE is high, lower byte of address from PC(Program Counter) is placed on the multiplexed data/address bus.
• after checking the status of READY pin, RD(bar) goes low the opcode is placed on the data bus, This state continues in the 3rd T-State.
• The fourth T-state is used to decode the instruction and to generate the relevant control signals. The state of the address bus is unspecified( This T-state is used by some DMA controllers to transfer data in hidden/transperant mode)
• IO/M(bar)= 0
• S1=1 S0=1

Memory Read (for 1 byte)

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• Three T states, similar to the first 3 T states of opcode fetch( as first 3 states of opcode fetch is effectively memory read)
• IO/M(bar) = 0
• S1 = 1 S0 = 0

Memory Write(for 1 byte)

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• WR bar is used When data is placed on data bus.

IO Read and IO Write

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• Simlar to the above two, only IO/M(bar) = 1

These are the basic machine cycles you will require to draw timing diagrams for most instructions.

HOW TO DRAW TIMING DIAGRAM

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Now, to draw the timing diagram for any instruction you need to understand what exactly the instruction does.

A) MOV A,B

• Draw only opcode fetch(4 T Cycles)
• no further memory acces is required as operands specified in registers only

B) MVI A,32H

• Draw opcode fetch
• memory read as operand(1 byte) has to be fetched from memory

C) LXI H, 2000H

• Draw Opcode Fetch
• two memory Reads as two bytes, 00H and 20H, (lower byte fetched first) have to be read from memory.

D) STA 2000H

• This instruction stores the value of accumulator(8 bit) at the location specified.
• Opcode fetch
• Two Memory read (byte address)
• One Memory write (1 byte)
• 13 T-states 4+3+3+3
• During the memory write the address bus contains the address fetched by the memory read cycle earlier

F)JMP 16-bit address

• Opcode Fetch
• Two Memory Read ( 16 bit = 2 bytes)
• 10 T-states 4+3+3

I HOPE THIS ARTICLE HELPS......!!